Welcome to IEEE TCCA Email-Monthly, Nov. 2003: 1. HPCA-10: 10th International Symposium on High-Performance=20 Computer Architecture *Madrid, Spain, February 14-18, 2004,=20 *Call for Participation: http://www.ac.uma.es/hpca10/=20 2. New papers published online by Computer Architecture Letters *Website: http://www.comp-arch-letters.org/2003paps.html -submitted by: Kevin Skadron =20 3. ACSAC'2004: 9th Asia-Pacific Computer Systems Architecture Conference *Beijing, China, September 7 - 9, 2004 =20 *Submission Deadline: February 29, 2004 -Submitted by: Yuanyuan Yang -CALL FOR PAPERS: http://www.cse.unsw.edu.au/~acsac04 4. CAC'04: Workshop on Communication Architecture for Clusters *Santa Fe, New Mexico, April 26-30, 2004=20 *Submission Deadline: extended to Nov. 10, 2003 -Submitted by: Nectarios Koziris -CALL FOR PAPERS: http://www.cis.ohio-state.edu/~cac=20 5. HotLeakage v1.0 release -Submitted by: Kevin Skadron ------- * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members,=20 send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20 ----------------------------------------------------------------------- Qing (Ken) Yang, Professor =09 Distinguished Engineering Professor e-mail: qyang@ele.uri.edu =20 Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 =20 University of Rhode Island Fax (401) 782-6422 =20 Kingston RI. 02881 http://www.ele.uri.edu/~qyang = =20 ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Call for Participation HPCA-10 10th International Symposium on High-Performance Computer Architecture =20 Madrid, Spain February 14-18, 2004 =20 http://www.ac.uma.es/hpca10/ The International Symposium on High-Performance Computer Architecture provides a high quality forum for scientists and engineers to present their latest research findings in this rapidly changing field. Final program and information on tutorials can be found at: http://www.ac.uma.es/hpca10/program.html Information on workshops and tutorials is available at: http://www.csl.cornell.edu/~espeight/hpca10wkshps.html http://www.ac.uma.es/hpca10/tutorials.html Registration is now open. Early registration period ends Jan. 16, 2004. On-site registration may be required after Feb. 6, 2004. Please register following instructions at: http://www.ac.uma.es/hpca10/registration.html Hotel rooms are available at special rates for HPCA-10 conference attende= es in Madrid at several locations. Convenient transportation is available fr= om any of them to the conference site (UCM campus). For more details, please see: http://www.ac.uma.es/hpca10/hotel.html HPCA-10 conference and workshops will be held at Facultad de Informatica of the Universidad Complutense, in Madrid. For transportation details, please refer to: http://www.ac.uma.es/hpca10/travel.html Finally, to find out what you can see and do in Madrid, please visit: http://www.ac.uma.es/hpca10/madrid.html See you in Madrid! -------------------------------------------------------------------------= - New papers published online by Computer Architecture Letters Computer Architecture Letters announces our four most recent papers, which are publicly available at http://www.comp-arch-letters.org/2003paps.html. We continue to seek new submissions and remain committed to fast and accurate review. Our mean time to decision remains one month, with an acceptance rate of approximately 21%. For more information on submission, please see http://www.comp-arch-letters.org - A. Milenkovic, M. Milenkovic. "Stream-Based Trace Compression." Volume 2, Sep. 2003. - C. Zhang, F. Vahid, J. Yang, W. Najjar. "A Way-Halting Cache for Low-Energy High-Performance Systems." Volume 2, Sep. 2003.=20 - A. Cohen, L. Finkelstein, A. Mendelson, R. Ronen, D. Rudoy. "On Estimating Optimal Performance of CPU Dynamic Thermal Management." Volume 2, Oct. 2003. - A. Cristal, J. F. Martinez, J. Llosa, M. Valero. "A Case for Resource-conscious Out-of-order Processors." Volume 2, Oct. 2003.=20 Abstracts --------- A. Milenkovic, M. Milenkovic. "Stream-Based Trace Compression." Volume 2, Sep. 2003. Abstract: Trace-driven simulation has long been used in both processor and memory studies. The large size of traces motivated different techniques for trace reduction. These techniques often combine standard compression algorithms with trace-specific solutions, taking into account the tradeoff between reduction in the trace size and simulation slowdown due to decompression. This paper introduces SBC, a new algorithm for instruction and data address trace compression based on instruction streams. The proposed technique significantly reduces trace size and simulation time, and it is orthogonal to general compression algorithms. When combined with gzip, SBC reduces the size of SPEC CPU2000 traces 94-71968 times. C. Zhang, F. Vahid, J. Yang, W. Najjar. "A Way-Halting Cache for Low-Energy High-Performance Systems." Volume 2, Sep. 2003.=20 Abstract:=20 We have designed a low power four-way set-associative cache that stores the four lowest-order bits of all way=92s tags into a fully associative memory, which we call the halt tag array. The comparison of the halt tag array with the desired tag occurs concurrently with the address decoding that determines which tag and data ways to read from. The halt tag array pre-determines most tags that cannot match due to their low-order four bits mismatching. Further accesses to ways with known mismatching tags are then halted, thus saving power. Our halt tag array has the additional feature of using static logic only, rather than dynamic logic used in highly-associative caches, making our cache consumes even less power. Our result shows 55% savings of memory access related energy over a conventional four-way set-associative cache. We show nearly 2x energy savings compared with highly associative caches, while imposing no performance overhead and only 2% cache area overhead. A. Cohen, L. Finkelstein, A. Mendelson, R. Ronen, D. Rudoy. "On Estimating Optimal Performance of CPU Dynamic Thermal Management." Volume 2, Oct. 2003. Abstract: In this paper we focus on dynamic thermal management (DTM) strategies that use dynamic voltage scaling (DVS) for power control. We perform a theoretical analysis targeted at estimating the optimal strategy, and show two facts: (1) when there is a gap between the initial and the limit temperatures, it is best to start with a high (though not necessarily maximal) frequency and decrease it exponentially until the limit temperature is reached; (2) when being close to the limit temperature, the best strategy is to stay there. We use the patterns exhibited by the optimal strategy in order to analyze some existing DTM techniques. A. Cristal, J. F. Martinez, J. Llosa, M. Valero. "A Case for Resource-conscious Out-of-order Processors." Volume 2, Oct. 2003.=20 Abstract: Modern out-of-order processors tolerate long-latency memory operations by supporting a large number of in-flight instructions. This is achieved in part through proper sizing of critical resources, such as register files or instruction queues. In light of the increasing gap between processor speed and memory latency, tolerating upcoming latencies in this way would require impractical sizes of such critical resources. To tackle this scalability problem, we make a case for resource-conscious out-of-order processors. We present quantitative evidence that critical resources are increasingly underutilized in these processors. We advocate that better use of such resources should be a priority in future research in processor architectures. -------------------------------------------------------------------------= - =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D Ninth Asia-Pacific Computer Systems Architecture Conference=20 (ACSAC'2004) http://www.cse.unsw.edu.au/~acsac04 Beijing, China September 7 - 9, 2004 (Submission deadline: February 29, 2004)=20 Sponsored by National Natural Science Foundation of China, NICTA ICT Aust= ralia,=20 and School of CSE at UNSW and in cooperation with IEEE Technical Committe= e on Computer Architecture (TCCA) (pending) and Technical Committee on Paralle= l Processing (TCPP) (pending). The Ninth Asia-Pacific Computer Systems Architecture Conference (ACSAC'20= 04)=20 will be held in Beijing, China, during September 7 - 9, 2004. Authors are= =20 invited to submit full papers on all aspects of computer systems architec= ture,=20 including (but not limited to) the following: * Processor architectures and innovative microarchitectures * Parallel computer architectures and computation models * Reconfigurable and embedded architectures * Compiler/OS/hardware support for efficient memory systems * Hardware support for OS and compilers * Compiler techniques and tools to support instruction-level parallelism (ILP) and thread-level parallelism (TLP) * Architectural and compiler support for speculative processors * Power-efficient architectures=20 * Real-time architectures * High-performance I/O architectures=20 * Application-specific systems=20 * Novel architectures for emerging technologies and applications=20 * Impact of VLSI scaling techniques=20 * High-availability architectures=20 * Interconnection networks and network interfaces=20 * Innovative hardware/software trade-offs=20 * Compilers and tools for parallel computer systems=20 * Simulation and performance evaluation=20 * Benchmarking and measurement of real systems IMPORTANT DATES: ---------------- Submissions of Abstracts: February 22, 2004 (11:00PM AEDT) Submissions of Full Papers: February 29, 2004 (11:00PM AEDT) Author Notification: May 2, 2004 Camera-Ready Papers: May 30, 2004 Registration of One Author: July 15, 2004 GENERAL CHAIR: -------------- Weimin Zheng=20 Department of Computer Science and Technology Tsinghua University Beijing, China Tel: +86 10 6278 3505-3 Fax: +86 10 6277 1138 E-mail: zwm-dcs@tsinghua.edu.cn PROGRAM CHAIRS: --------------- Pen-Chung Yew=20 Department of Computer Science and Engineering University of Minnesota at Twin Cities =20 200 Union Street, SE =20 Minneapolis, MN 55455-0159, USA Tel: 612 625-0726/625-7387 Fax: 612 625-0572 Email: yew@cs.uwn.edu Jingling Xue=20 School of Computer Science and Engineering University of New South Wales, Australia Sydney, NSW 2052, Australia E-mail: jxue@cse.unsw.edu.au Tel: +61 2 9385 4889 Fax: +61 2 9385 5995 Email: jxue@cse.unsw.edu.au PROGRAM COMMITTEE: ------------------ - Lars Bengtsson (Chalmers University, Sweden) =20 - Sangyeun Cho (Samsung Electronics, Co., Korea) - Lynn Choi (Korea University, Korea) - Rudolf Eigenmann (Purdue University, USA) - Jean-Luc Gaudiot (University of California, Irvine, USA) - Antonio Gonzalez (Universitat Politecnica de Catalunya & Intel Labs, Sp= ain) - Gernot Heiser (NICTA ICT Australia, Australia) - Chris Jesshope (University of Hull, UK) - Angkul Kongmunvattana (University of Nevada, Reno, USA)=20 - Feipei Lai (National Taiwan University) - Zhiyong Liu (National Natural Science Foundation of China, China) - Guei-Yuan Lueh (Intel, USA) - John Morris (Chung-Ang University, Korea/University of Auckland, New Ze= aland) - Tadao Nakamura (Tohoku University, Japan) - Yukihiro Nakamura (Kyoto University, Japan) - Amos Omondi (Flinders University, Australia) - Lalit M. Patnaik (Indian Institute of Science, Bangalore, India) - Jih-Kwon Peir (University of Florida, USA) - Ronald Pose (Monash University, Australia) - Depei Qian (Xian Jiaotong University, China) - Stanislav G. Sedukhin (University of Aizu, Japan) - Naofumi Takagi (Nagoya University, Japan) - Zhimin Tang (Chinese Academy of Sciences, China) - Rajeev Thakur (Argonne National Laboratory, USA) - Theo Ungerer (University of Augsburg, Germany) - Winfried W. Wilcke (IBM Research, USA) - Weng Fai Wong (National University of Singapore, Singapore) - Chengyong Wu (Chinese Academy of Sciences, China) - Ming Xu (National University of Defense Technology, China) - Yuanyuan Yang (State University of New York at Stony Brook, USA) - Rumi Zahir (Intel, USA)=20 - Chuanqi Zhu (Fudan University, China) PROCEEDINGS AND SUBMISSION GUIDELINES: -------------------------------------- Accepted and presented papers are planned to be published in the=20 Springer-Verlag "Lecture Notes in Computer Science" series.=20 Prospective authors are invited to submit a 100 - 200 word abstract=20 (including between four and six keywords and the e-mail address of=20 the corresponding author) and a full paper in *English* (not to exceed 6000 words) presenting original and unpublished research results=20 and experience. Papers will be selected based on their originality,=20 timeliness, significance, relevance, and clarity of presentation. It is=20 understood that papers in new areas are likely to contain less quantitati= ve=20 evaluations and comparisons than those in more established areas. Submissions will be carried out electronically via the Web via a link=20 found at the conference web page http://www.cse.unsw.edu.au/~acsac04/. =20 Papers must be submitted in PDF (preferably) or Postscript that is interpretable by Ghostscript. Excessively long papers will be rejected=20 immediately by the Program Chairs. Submissions imply the willingness of at least one author to register,=20 attend the conference, and present the paper.=20 There will be two best student paper awards to recognise distinguished=20 student research. At the conference's submission page, please tick whethe= r=20 your paper is a student paper. The criteria for student papers will be=20 available shortly at the conference web site. -------------------------------------------------------------------------= - CAC '04: Workshop on Communication Architecture for Clusters =20 submitted by Nectarios Koziris Call For Papers http://www.cis.ohio-state.edu/~cac =20 ------------------------------------------------------------------------ Due to multiple requests, the paper submission deadline has been=20 extended to Nov. 10, 2003. The perspective authors are requested to submit an abstract, title, and author information by Nov. 7, 2003.=20 ------------------------------------------------------------------------ Workshop on Communication Architecture for Clusters (CAC '04) To be held in Conjunction with=20 Int'l Parallel and Distributed Processing Symposium (IPDPS '04) Santa Fe, New Mexico Eldorado Hotel, April 26-30, 2004=20 ------------------------------------------------------------------------ - Due to multiple requests, the paper submission deadline has been=20 extended to Nov. 10, 2003. The perspective authors are requested to submit an abstract, title, and author information by Nov. 7, 2003.=20 ------------------------------------------------------------------------ - THEME: The availability of commodity PCs/workstations and high-speed networks (Local Area Networks and System Area Networks) at low prices enabled the development of low-cost clusters. These clusters are being targeted for support of traditional high-end computing applications as well as emerging applications, especially those requiring high-performance servers. Designing high-performance and scalable clusters for these emerging applications requires design and development of high-performance communication and I/O subsystems, low-overhead programming environment support and support for Quality of Service (QoS). New standards such as InfiniBand Architecture (IBA) and PCI Express AS, and availability of high-speed networking products (Myrinet, Quadrics, IBA 4X, and 10GigEthernet) are providing exciting ways to design high-performance communication and I/O architectures for clusters. A large number of research groups from academia, industry, and research labs are currently engaged in the above research directions. The goal of this workshop is to bring together researchers and practitioners working in the areas of communication, I/O, and architecture to discuss state-of-the-art solutions as well as future trends for designing scalable, high-performance, and cost-effective communication and I/O architectures for clusters. The first three workshops in this series (CAC '01, CAC '02, and CAC '03) were held in conjunction with IPDPS conferences, and they were very successful. The CAC '04 workshop plans to continue this tradition. TOPICS OF INTEREST: =20 Topics of interest for the workshop include but are not limited to: 1. Router/switch, network, and network-interface architecture for supporting efficient point-to-point communication, collective=20 communication, and I/O at intra-cluster and inter-cluster levels. 2. Design, development, and implementation of low-level communication and I/O protocols (GM, TCP/IP, VAPI, SDP, DAPL, SRP, iSCSI, RDMA over IP, etc) on different networking and interconnect technologies (such as Myrinet, 10Gigabit Ethernet, InfiniBand, Quadrics, TCP Offload Engine, etc.). 3. High-performance implementation of different programming layers (Message Passing Interface (MPI), Distributed Shared Memory such=20 as TreadMarks, Get/Put, Global Arrays, sockets, etc.) and File=20 Systems (such as PVFS and DAFS). 4. Communication and architectural issues related to switch organization, flow control, congestion control, routing and deadlock-handling, load balancing, reliability, and QoS support. 5. Strategies, algorithms, and protocols for management of communication resources, including topology discovery, hot update/replacement of components, dynamic reconfigurations, etc. 6. Performance evaluation and tools for different application areas, including interprocessor communication and I/O, etc.=20 Results of both theoretical and practical significance will be considered. PROCEEDINGS: The proceedings of this workshop will be published together with the proceedings of other IPDPS '04 workshops by the IEEE Computer Society Press. PAPER SUBMISSIONS: We are planning a purely web submission and review process. Authors are requested to submit papers (in PDF format) not exceeding 10 single-spaced pages, including abstract, five key words, contact address, figures, and references. Detailed instructions on web submissions will be available soon. Note: the PDF file must be viewable using the ``acroread'' tool. It is also important, when creating your PDF file, to use a page size of 8.5x11 inches (LETTER sized output not A4), since an A4 sized page may be truncated on a LETTER sized printer. SCHEDULE: Abstract submission: October 30, 2003 (extended to Nov. 7, 2003) Paper submission: November 3, 2003 (extended to Nov. 10, 2003)=20 Notification of acceptance: December 19, 2003=20 Camera-ready due: January 23, 2004=20 WORKSHOP CO-CHAIRS: Dhabaleswar K. Panda (Ohio State),=20 Jose Duato (Tech. Univ. of Valencia, Spain), and Craig Stunkel (IBM TJ Watson Research Center) PROGRAM COMMITTEE: =20 Bulent Abali (IBM TJ Watson) Mohammad Banikazemi (IBM TJ Watson) Angelos Bilas (Univ. of Toronto, Canada) Alan Benner (IBM) Ron Brightwell (Sandia National Lab) Darius Buntinas (Argonne National Lab)=20 Toni Cortes (UPC, Spain) Wu-Chun Feng (Los Alamos National Lab) Jose Flich (Tech. Univ. of Valencia, Spain) Mitchell Gusat (IBM, Zurich) Mark Heinrich (Cornell Univ.) Manolis G.H. Katevenis (FORTH and Univ. of Crete, Greece) Nectarios G. Koziris (National Technical Univ. of Athens, Greece) Mario Lauria (Ohio State) Olav Lysne (Univ. of Oslo, Norway) Arthur (Barney) Mccabe (Univ. of New Mexico) Pankaj Mehra (HP) Shubu Mukherjee (Intel) Jarek Nieplocha (Pacific Northwest National Lab) Scott Pakin (Los Alamos National Lab) Fabrizio Petrini (Los Alamos National Lab) Greg Pfister (IBM) Timothy Pinkston (Univ. of Southern California) Wolfgang Rehm (Tech. Univ. of Chemnitz, Germany) Antonio Robles (UPV, Spain) Tom Rokicki (Instantis) Reza Rooholamini (Dell) Evan Speight (Cornell) Thomas M. Stricker (ETH, Zurich) Peter Varman (Rice Univ. and NSF) Pete Wyckoff (Ohio Supercomputer Center) Mazin Yousif (Intel) PUBLICITY COORDINATORS: Darius Buntinas (Argonne National Lab) Nectarios G. Koziris (National Technical Univ. of Athens, Greece) ADDITIONAL INFORMATION: On the World Wide Web, see http://www.cis.ohio-state.edu/~cac for the latest information about this workshop. Alternatively, you can send e-mail to cac@cis.ohio-state.edu. -------------------------------------------------------------------------= - HotLeakage v1.0 release ----------------------- We would like to announce the release of "HotLeakage" -- an architectural model for subthreshold and gate leakage that we have developed here at the University of Virginia. The most important features of HotLeakage are the explicit inclusion of temperature, voltage, gate leakage, and parameter variations, and the ability to recalculate leakage currents dynamically as temperature and voltage change due to operating conditions, DVS, etc. HotLeakage provides default settings from BSIM3 and BSIM4 data for 180nm through 70nm technologies for modeling caches and other structures, and provides a simple interface for selecting alternate parameter values and for modeling alternative microarchitecture structures. HotLeakage also provides SimpleScalar models for several extant cache leakage control techniques (namely gated-Vss, drowsy cache, and MTCMOS/RBB), with an interface for adding further techniques. HotLeakage is currently a semi-independent module for use with SimpleScalar. Because it is a distinct module with its own interface, it should be fairly easy to port to other simulators. =20 Because sub-threshold leakage currents are exponentially dependent on temperature and voltage, because gate leakage is growing so rapidly, and because parameter variations can have a profound effect on simulation accuracy, we hope that HotLeakage will serve as a useful tool for microarchitects to more accurately evaluate issues pertaining to leakage power. More information can be found on the HotLeakage website at http://lava.cs.virginia.edu/HotLeakage We maintain a mailing list for user questions and feedback, which can be subscribed to at the same website. Kevin Skadron, Mircea R. Stan, Dharmesh Parikh, Yan Zhang, Yingmin Li, and Karthik Sankaranarayanan Depts. of Computer Science, Electrical and Computer Engineering University of Virginia =20 -------------------------------------------------------------------------= - * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20